Integrated circuit field effect transistors are widely used in microelectronic devices. As the integration density of integrated circuits continues to increase, the size of the field effect transistors in the integrated circuit may continue to decrease. Unfortunately, as the size continues to decrease below half micron channel length, short channel effects arise that may degrade the performance of the field effect transistor. Short channel effects may occur when the depletion regions of the source/drain regions of the field effect transistor expand into the channel to reduce the length of the effective channel. This may cause the threshold voltage to drop and/or other undesired effects.
In order to reduce short channel effects it is known to reduce the thickness of the gate insulating layer, the width of the depletion region under the gate and/or the doping concentration of the integrated circuit substrate. It is also known to provide shallow source/drain junction regions.
It is also known to provide integrated circuit field effect transistors with both lightly doped and heavily doped source/drain regions. It will be understood that the terms "lightly doped" and "heavily doped" refer to doping levels relative to one another. Thus, for example, lightly doped source/drain structures also include moderately doped source/drain structures that can provide a higher doping level than a conventional lightly doped source/drain structure while still being lightly doped relative to the heavily doped source/drain structure. Unfortunately, the increased doping level in a moderately doped source/drain structure may worsen short channel effects.
A conventional fabrication method for integrated circuit field effect transistors including both lightly doped source/drain regions and heavily doped source/drain regions is described in U.S. Pat. No. 5,710,450 to Chau et al., entitled "Transistor with Ultra Shallow Tip and Method of Fabrication." In such a conventional integrated circuit field effect transistor fabrication method, a gate insulating film is formed on an integrated circuit substrate such as a silicon semiconductor substrate. A gate electrode, preferably comprising polysilicon, is formed on the gate insulating layer. Then, lightly doped source/drain regions having shallow junctions are formed using the gate electrode as an ion implantation mask. Gate spacers are formed on the sidewalls of the gate electrodes. Heavily doped source/drain regions are formed, that are heavily doped relative to the lightly doped source/drain regions, using the gate electrode and the gate spacers as an ion implantation mask. The resultant structure is thermally treated thereby forming an integrated circuit field effect transistor. See also U.S. Pat. No. 5,215,937 to Erb et al., entitled "Optimizing Doping Control in Short Channel MOS."
In a conventional method, after the shallow junction of the lightly doped source/drain (including a moderately doped source/drain) is formed, gate spacer formation may be performed at temperatures of between about 450.degree. C. to about 600.degree. C. Moreover, after the ion implantation of the heavily doped source/drain region, a thermal anneal may be performed at about 1000.degree. C. Unfortunately, the gate spacer formation process and/or the thermal treatment may cause redistribution of silicon atoms and diffusion of dopants within the integrated circuit substrate. Short channel effects may therefore increase and the performance of the integrated circuit field effect transistor may degrade.